This invention relates to digital data transmission systems and more particularly, to a circuit for deriving timing signals from a serial digital data stream and a method therefor whereby the timing signals may be subsequently utilized by a receiver to decode and deserialize the received data stream.
In transmitting serial digital data, it is necessary to provide a series of clock pulses in addition to the data pulses in order to synchronize the coding of the transmitted serial digital data at a receiving terminal or the receiver. In prior-known transmitting schemes, two transmission lines or paths, or two channels were required for this purpose, one for the data signal and one for the clocking signal. In attempting to avoid the requirement for a dual transmission path (or two channels), self-clocking codes evolved as a result of combining the clock and data signals. The Manchester code is one such self-clocking code. Manchester encoders accept clock and data and combine them into a single output which may be transmitted by a single transmission line to the receiving terminal. When the self-clocking data (i.e., the serial digital data stream) arrives at the receiving terminal, it is processed by a decoder which extracts separately both data and clock from the input self-clocking code.
The clock recovery circuits of the prior art generally are formed by directing the serial digital data stream into AND or NAND gates causing a clock output, and when the conditions for setting disappear, the output resets. The circuit of the present invention requires a specific condition, or set of conditions, to set a latch and another condition, or set of conditions, to reset the latch yielding a symmetrical recovered clock. As a result of utilizing a latch requiring specific set conditions and specific reset conditions, there is provided by the circuit of the current invention a high-speed real time clock recovery circuit. In addition, the circuit of the current invention provides a significant desensitivity to delay line tap to tap variations and further yields a recovered clock symmetry that is less sensitive to the bit skew of the raw input serial digital data stream. Further, the circuit of the current invention generates a signal indicative of when a low frequency has occurred in the serial digital data stream, which signal is subsequently utilized in a data recovery circuit for Manchester code or diphase code.